1. Field of the Invention
This invention relates to vias formed in integrated circuit devices. More particularly, this invention relates to an improved via formed in a planarized dielectric used to electrically separate adjacent metal layers in integratd circuit devices.
2. Description of the prior Art
Multilayer integrated circuit devices having a plurality of metal layers separated by dielectric layers utilize etched openings or vias through the dielectric layer to electrically interconnect selected portions of one metal layer with selected portions of an adjacent metal layer. The portion of the lower metal layer to which contact is to be made may comprise a narrow strip or line of metal of, for example, 2 to 4 micron width. It is, therefore, important that the width of the opening etched through the overlying dielectric layer does not exceed this dimension, or even overlap the width of the underlying metal to avoid contacting other portions of the underlying integrated circuit structure with the etching means used to form the via.
The use of narrow openings, however, presents difficulty in the subsequent metallization or filling of the via with metal, as shown in FIG. 1A. In this figure, a lower metal line 10 is formed by masking and etching a metal layer placed over an underlying integrated circuit structure 2. Dielectric material 14 is placed over metal line 10, and an opening or bore 20 is then etched through dielectric 14 which is subsequently filled with metal. This forms a via which provides interconnection of metal line 10 with a second metal layer 30 which is deposited over dielectric layer 14. However, the upper corners 24 of the bore 20 provide a constriction which results in the necking in at 34 of the metal used to fill bore 20 to interconnect metal line 10 with upper metal layer 30.
As shown in FIG. 1B, a successful prior art approach to solving this problem was to etch a first narrow opening 20 and then to subsequently remask dielectric laYer 14 with a mask providing a larger opening followed by a subsequent anisotropic etch to provide opening 22. The corners 24' of dielectric 14. thus, were further apart, the depth of opening 22 was made shallower, and the constrictions or necking in problem was thereby reduced. This method was either practiced using a single dielectric layer or in combination with a multilayer dielectric deposition and planarization such as described and claimed in U.S. Pat. No. 4,481,070 invented by two of us and assigned to the assignee of this invention, and cross-reference to which is hereby made.
This prior art solution to the problem, however, resulted in the need for two separate masking steps to etch the two opening widths shown in FIG. 1B. Since each masking step is, in reality, a number of steps to apply, expose, and develop the photo-resist, etch the dielectric, and then remove the photoresist coating, followed by a repeat of the foregoing steps, the solution to the problem was very inefficient. The additional steps not only involved extra costly time, effort, and material, but had an additional negative impact on the yield.
It, therefore, would be desirable to reduce the problem of the necking in or shadowing of the metallization of the via without the need for two separate masking steps.